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Search results for biblio_year:1991
Filters: 1 is biblio_year:2006 and 2 is biblio_type:Journal Article and 3 is biblio_type:Proceedings, refereed and 4 is field_research_area:1 and Author is José Flich  [Reset Search]
2013
B. Bogdanski, B. D. Johnsen, S. Reinemo and J. Flich. Making the Network Scalable: Inter-Subnet Routing in InfiniBand In Proceedings from the 19th International Euro-Par Conference on Parallel Processing, Edited by B. M. F. Wolf and D. a. Mey. Vol. 8097. Lecture Notes in Computer Science 8097. Springer Berlin Heidelberg, 2013.
2011
J. Escudero-Sahuquillo, E. G. Gran, P. J. García, J. Flich, T. Skeie, O. Lysne, F. J. Quiles and J. Duato. Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks In International Conference on Parallel Processing, ICPP 2011, Edited by R. Bilof. IEEE Computer Society, 2011.PDF icon Simula.simula.834.pdf (645.59 KB)
S. R. Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato. "Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems." IEEE Transactions on Computed Aided Design 30 (2011): 534-547.
F. O. Sem-Jacobsen, S. R. Mocholi and T. Skeie. IFDOR - Dynamic Rerouting On-Chip In Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, Edited by J. Flich and D. Bertozzi. New York, USA: ACM, 2011.
2010
S. R. Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato. Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing In NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, Edited by I. C. Society. IEEE Computer Society, 2010.
J. Flich, S. R. Mocholi, A. Roca and S. Medardoni. "Routing Algorithms and Mechanisms." In Designing Network On-Chip Architectures in the Nanoscale Era, edited by D. B. J. Flich, 135-174. Chapman & Hall/CRC Computational Science, 2010.
2008
O. Lysne, J. M. Montanana, J. Flich, J. Duato, T. M. Pinkston and T. Skeie. "An Efficient and Deadlock-Free Network Reconfiguration Protocol." IEEE Transactions on Computers 57 (2008): 762-779.
J. Flich, S. R. Mocholi and J. Duato. An Efficient Implementation of Distributed Routing Algorithms for NoCs In Second ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008, Edited by I. C. Society. IEEE Computer Society, 2008.
J. Flich, S. R. Mocholi, J. Duato, T. Sødring, Å. G. Solheim, T. Skeie and O. Lysne. "On the Potential of NoC Virtualization for Multicore Chips." Scalable Computing: Practice and Experience 9 (2008): 165-177.
J. Flich, S. R. Mocholi, J. Duato, T. Sødring, Å. G. Solheim, T. Skeie and O. Lysne. On the Potential of NoC Virtualization for Multicore Chips In International Workshop on Multi-Core Computing Systems (MuCoCoS'08), Edited by S. Pllana. IEEE, 2008.
2007
S. Reinemo, T. Skeie, A. Mejía, J. Flich and J. Duato. Boosting Ethernet Performance by Segment-Based Routing In Proceedings of the 15th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2007), Edited by P. D'Ambra and M. R. Guarracino. IEEE Computer Society Press, 2007.PDF icon Reinemo.2007.1.pdf (182.96 KB)
2006
M. E. Gómez, N. A. Nordbotten, J. Flich, P. Lopez, A. Robles, J. Duato, T. Skeie and O. Lysne. "A Routing Methodology for Achieving Fault Tolerance in Direct Networks." IEEE Transactions on Computers 55 (2006): 400-415.
A. Mejía, J. Flich, J. Duato, S. Reinemo and T. Skeie. Segment-Based Routing: an Efficient Fault-Tolerant Routing Algorithm for Meshes and Tori In 20th IEEE International Parallel & Distributed Processing Symposium, Edited by S. Ali. Washington, USA: IEEE Computer Society, 2006.PDF icon Mejia.2006.1.pdf (249.68 KB)
G. Mora, J. Flich, J. Duato, P. Lopez and O. Lysne. Towards and Efficient Switch Architecture for High-Radix Switches In ACM/IEEE Symposium on Architectures for Networking and Communications Systems, Edited by M. Dubois and W. Eatherton. ACM Press, 2006.
2004
O. Lysne, J. M. Montanana, T. M. Pinkston, J. Duato, T. Skeie and J. Flich. Simple Deadlock-Free Dynamic Network Reconfiguration In High Performance Computing - HiPC 2004: 11th International Conference, Bangalore, India, December 19-22, 2004, Edited by V. P. L. Bouge. Lecture Notes in Computer Science. Springer Verlag, 2004.