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Filters: Author is Federico Silla [Clear All Filters]
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems." IEEE Transactions on Computed Aided Design 30 (2011): 534-547."
Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing In NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, Edited by I. C. Society. IEEE Computer Society, 2010.
Yield-Oriented Evaluation Methodology of Network-on-Chip Routing Implementations In SOC'09 Proceedings of the 11th international conference on System-on-chip, Edited by IEEE. IEEE, 2009.