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publications
Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix–vector multiplication
Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix–vector multiplication
Authors
J. D. Trotter
,
J. Langguth
and
X. Cai
Status
Published
Publication type
Journal Article
Year of publication
2020
Journal
Journal of Parallel and Distributed Computing
Publisher
Elsevier
URL
http://www.sciencedirect.com/science/article/pii/S0743731520302999
DOI
https://doi.org/10.1016/j.jpdc.2020.05.020
Citation key
15800
Google Scholar
BibTex