UPS: Unlocking the Power of Spatial Computing using Tile-Centric AI Accelerators

Tile-centric AI accelerators, such as Graphcore IPUs and Cerebras systems, represent a major recent development in computer hardware. These processors use on-chip SRAM to provide extremely low latency and high memory bandwidth, making them well suited for graph algorithms and other irregular, data-intensive workloads.

Despite their potential, programming such devices remains challenging, particularly due to diverse hardware designs and programming interfaces. This limits their adoption beyond standard deep learning applications.

The UPS project aims to address this challenge by developing a common framework of communication routines and graph primitives for tile-centric AI accelerators, similar to the role MPI played in making cluster computing widely accessible. The project combines theoretical work on spatial models of computation with practical benchmarking and low-level implementation, establishing a foundation for broader and more efficient use of these emerging architectures.

Funding

This project is funded through the Research council of Norway's funding scheme “Researcher projects for ICT Renewal and Development” (forskningsradet.no).

Partners

• Simula Research Laboratory (Norway), coordinator
• UiB (Norway)
• UiO (Norway)
• Pacific Northwest National Laboratory (USA)
• Karlsruhe Institute of Technology (Germany-9