Scalable RISC-V DPU Cluster on AMD Xilinx Alveo U280 Boards
The primary goal of this master's thesis is to design and implement a multicore RISC-V soft processor DPU, preferably with RV64GC RISC-V BOOM quadcore with integrated 100Gbps Ethernet and Aurora interfaces. Four of these highly capable boards will be clustered to create a powerful compute platform specifically optimized for distributed machine learning workloads, or a HPC workload.
This master's thesis offers a unique opportunity for two students to implement a RISC-V based Data Processing Unit (DPU) soft processor on AMD Xilinx Alveo U280 boards. The core of this project involves clustering four of these cards together using 100Gbps Ethernet and/or Aurora to perform advanced computational tasks, particularly in distributed machine learning or a HPC workload. Students will have the flexibility to either leverage Xilinx's custom Microblaze-V IP and PetaLinux, or explore open-source multicore RISC-V implementations such as Berkeley Rocket Chip, alongside open-source Linux distributions like Debian or Fedora. The project will also involve utilizing Vitis for the development of distributed machine learning applications on these DPUs.
Goal
The primary goal of this master's thesis is to design and implement a multicore RISC-V soft processor DPU, preferably with RV64GC RISC-V BOOM quadcore with integrated 100Gbps Ethernet and Aurora interfaces. Four of these highly capable boards will be clustered to create a powerful compute platform specifically optimized for distributed machine learning workloads, or a HPC workload.
Learning outcome
Through the successful completion of this thesis, students will gain invaluable expertise in several cutting-edge areas:
- FPGA Board Expertise: Deep understanding of state-of-the-art Xilinx Alveo FPGA boards, including their architecture and capabilities.
- Soft Processor Implementation: Hands-on experience with implementing soft processors, mastering DMA functionalities (XDMA, QDMA) for host-to-card (h2c) and card-to-host (c2h) data transfers, and utilizing High Bandwidth Memory (HBM) support.
- High-Performance Interconnects: Practical knowledge of High-Performance Computing (HPC) interconnects, including 100Gbps Ethernet and Xilinx's proprietary Aurora RDMA protocol. Some experience with network switches is an advantage.
- FPGA Development Toolchain: Proficiency with industry-standard FPGA development tools such as Vivado and Vitis, alongside a strong grasp of FPGA fundamentals and programming.
- Xilinx IP and Ecosystem: In-depth understanding of various Xilinx Intellectual Properties (IPs) like AXI, XDMA, QDMA, and the PetaLinux embedded Linux distribution.
- Collaborative Research Environment: Opportunity to collaborate with experienced engineers and researchers from Simula and UiT, utilizing Simula’s eX3 FPGA POD, which features advanced Xilinx Alveo U250 and U280 boards clustered with Mellanox SN2100 100Gbps and Quantum Infiniband switches.
The skills developed through this thesis are highly sought after by leading Norwegian tech companies, making successful graduates exceptionally employable.
Qualifications
- Candidates should possess a strong interest in learning fundamental concepts related to FPGA design using Xilinx Vivado and Vitis tools, as well as the RISC-V Instruction Set Architecture (ISA). While beneficial, prior knowledge of HPC networking and Linux operating systems is not mandatory. Comprehensive support will be provided to help students quickly get started and engage in hands-on work with Simula's FPGA POD.
Supervisors
- Håkon Kvale Stensland
- Tor H. Larsen (daily contact)
- Masoud Hemmatpour
Collaboration partners
- UiO