AuthorsS. R. Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato
TitleCost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
AfilliationCommunication Systems, Communication Systems
StatusPublished
Publication TypeJournal Article
Year of Publication2011
JournalIEEE Transactions on Computed Aided Design
Volume30
Number4
Pagination534-547
Date PublishedApril
PublisherIEEE
Abstract

The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.

DOI10.1109/TCAD.2011.2119150
Citation KeySimula.simula.512