AuthorsT. Skeie, F. O. Sem-Jacobsen, S. R. Mocholi, J. Flich, D. Bertozzi and S. Medardoni
EditorsJ. Nurmi, J. Takala and O. Vainio
TitleFlexible DOR Routing for Virtualization of Multicore Chips
Afilliation, Communication Systems
StatusPublished
Publication TypeProceedings, refereed
Year of Publication2009
Conference NameInternational Symposium on System-on-Chip
Date PublishedOctober
PublisherIEEE
ISBN Number978-1-4244-4465-6
Abstract

The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (NoC). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.

Citation KeySimula.ND.367