AuthorsK. R. Stokke
TitleHigh-Precision Power Modelling and Optimisation of the Tegra K1 Heterogeneous Multicore Architecture
AfilliationCommunication Systems
Project(s)No Simula project
StatusPublished
Publication TypePhD Thesis
Year of Publication2017
Degree awarding institutionFaculty of Mathematics and Natural Sciences at the University of Oslo
DegreePhD
Number of Pages194
PublisherUniversity of Oslo
Place PublishedFaculty of Mathematics and Natural Sciences, University of Oslo
Thesis TypePhD
Abstract

Modern, mobile devices such as smart phones, laptops or even drones fulfill many of the users’ need for games, social, work and other activities. Much of the processing done on these devices is related to multimedia, for example with applications such as Snapchat, Pokemon Go, Ingress and YouTube. However, mobile devices are constrained with a limited energy supply, where the evolution in battery energy density has not followed the power requirements of modern processors. These integrate Systems-on-Chip (SoC), such as the Tegra K1 SoC, that feature a range of different hardware accelerators, general purpose processors and advanced power management mechanisms such as frequency scaling. The challenge for system architects and programmers is thus to understand how to develop, distribute and schedule multimedia workloads across the heterogeneous, multicore processors. However, manually measuring power usage of running software on different processors is unfeasible, and separating the power usage of an application’s instructions and memory usage from other processes and power components is very hard. Models for power are therefore necessary to understand the relation between energy consumption, software activity and power saving mechanisms. However, the state-of-the-art power modelling methods that exist in the literature fail to give an accurate view of the energy consumption of SoCs such as the Tegra K1. In this thesis, we therefore develop an improved power modelling methodology that is able to predict power usage of the Tegra K1 with close to 100 % accuracy. By tracking platform frequencies and voltages, power- and clock-gating as well as fine-grained hardware activity measurements, our model provides detailed insight into static and dynamic power components of the Tegra K1’s heterogenous processors and memory. By using our power model, we identify main reasons behind energy-inefficiency in processors, analyse and optimise the energy consumption of kernel drivers, and study the effects of programming using different types of instructions, noncoherent caches and load-balancing between heterogeneous processors.

URLhttp://folk.uio.no/krisrst/thesis.pdf