|Authors||K. R. Stokke, H. K. Stensland, P. Halvorsen and C. Griwodz|
|Editors||S. Le Beux|
|Title||High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture|
|Publication Type||Proceedings, refereed|
|Year of Publication||2016|
|Conference Name||10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)|
Energy efficiency is an important issue for many embedded systems, where limited battery lifetime and power- hungry hardware constrain the usefulness of such devices. Modern Systems-on-Chip (SoCs) such as the Tegra K1 employ advanced power management capabilities such as two CPU clus- ters, clock-gating, power-gating and dynamic frequency tuning to meet application demands. At design or runtime phases, it is challenging for system architects and software developers to understand the effects that these mechanisms have in terms of power and performance in all parts of the system. This is especially because it is impossible to measure directly the power usage of cores, caches, memory and other hardware components. Rate-based power models are often proposed as a solution for this, but unfortunately these can mispredict substantially on the Tegra K1 up to 30 %. In this paper, we propose a power modelling method for the Tegra K1 CPU which overcomes the limitations of the most common types of models found in literature, but still only requires power measurement of the board. Through extensive empirical validation we demonstrate an accuracy which is close to 100 %. Through preliminary experiments we show that our methodology is able to capture instruction power of individual system processes and applications and produce detailed power breakdowns of all components in the system.