|Authors||J. D. Trotter, J. Langguth and X. Cai|
|Title||Quantifying data traffic of sparse matrix-vector multiplication in a multi-level memory hierarchy|
|Project(s)||Meeting Exascale Computing with Source-to-Source Compilers|
|Year of Publication||2018|
|Place Published||London, UK|
Sparse matrix-vector multiplication (SpMV) is the central operation in an iterative linear solver. On a computer with a multi-level memory hierarchy, SpMV performance is limited by memory or cache bandwidth. Furthermore, for a given sparse matrix, the volume of data traffic depends on the location of the matrix non-zeros. By estimating the volume of data traffic with Aho, Denning and Ullman’s page replacement model , we can locate bottlenecks in the memory hierarchy and evaluate optimizations such as matrix reordering. The model is evaluated by comparing with measurements from hardware performance counters on Intel Sandy Bridge.