AuthorsJ. D. Trotter, J. Langguth and X. Cai
TitleQuantifying data traffic of sparse matrix-vector multiplication in a multi-level memory hierarchy
AfilliationScientific Computing
Project(s)Meeting Exascale Computing with Source-to-Source Compilers
StatusPublished
Publication TypePoster
Year of Publication2018
Date Published06/2018
Place PublishedLondon, UK
Abstract

Sparse matrix-vector multiplication (SpMV) is the central operation in an iterative linear solver. On a computer with a multi-level memory hierarchy, SpMV performance is limited by memory or cache bandwidth. Furthermore, for a given sparse matrix, the volume of data traffic depends on the location of the matrix non-zeros. By estimating the volume of data traffic with Aho, Denning and Ullman’s page replacement model [1], we can locate bottlenecks in the memory hierarchy and evaluate optimizations such as matrix reordering. The model is evaluated by comparing with measurements from hardware performance counters on Intel Sandy Bridge.

[1]: Alfred V. Aho, Peter J. Denning, and Jeffrey D. Ullman. 1971. Principles of Optimal Page Replacement. J. ACM 18, 1 (January 1971), pp. 80-93.

Citation Key26157