AuthorsJ. D. Trotter, J. Langguth and X. Cai
TitleCache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix–vector multiplication
AfilliationScientific Computing
Project(s)Meeting Exascale Computing with Source-to-Source Compilers, Department of High Performance Computing
Publication TypeJournal Article
Year of Publication2020
JournalJournal of Parallel and Distributed Computing
Date Published06/2020
KeywordsAMD Epyc, Cache simulation, Intel Xeon, Performance model, Sparse matrix–vector multiplication

Parallel computations with irregular memory access patterns are often limited by the memory subsystems of multi-core CPUs, though it can be difficult to pinpoint and quantify performance bottlenecks precisely. We present a method for estimating volumes of data traffic caused by irregular, parallel computations on multi-core CPUs with memory hierarchies containing both private and shared caches. Further, we describe a performance model based on these estimates that applies to bandwidth-limited computations. As a case study, we consider two standard algorithms for sparse matrix–vector multiplication, a widely used, irregular kernel. Using three different multi-core CPU systems and a set of matrices that induce a range of irregular memory access patterns, we demonstrate that our cache simulation combined with the proposed performance model accurately quantifies performance bottlenecks that would not be detected using standard best- or worst-case estimates of the data traffic volume.

Citation KeyTROTTER2020189